In the fabrication of integrated circuits (ICs) or chips, there are often conflicting requirements in different regions of the IC. Such conflicts increase the complexity of the fabrication process, resulting in the need for additional process steps.
This problem can be illustrated by the differing requirements in different regions of a memory IC such as a dynamic random access memory (DRAM) or merged DRAM-logic (embedded DRAM) chip. For example, deep junctions with self-aligned silicides (salicides) are desired in the support or logic regions to minimize series resistance. However, shallow junctions with low dose implants and no silicides are desired in the array in order to minimize junction leakage.
Conventional techniques of resolving such conflict in the array and support or logic regions require additional masking steps to block deep junction implants and silicide formation in the array. Such techniques add complexity and cost to the manufacturing process, as well as increase raw process time (RPT).
As apparent from the above discussion, it is desirable to provide a more efficient and simplified technique of addressing the conflicting needs of the different chip regions.